View ADP1864-15_8248130.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

constant frequency current - mode step - dow n dc - to - dc controller in tsot data sheet adp1864 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog dev ices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 C 2012 analog devices, inc. all rights reserved. features wide input voltage range: 3.15 v to 14 v wide output voltage range: 0.8 v to input voltage pin - to - pin compatible with ltc1772, ltc3801 up to 94% efficiency 0.8 v 1.25% reference accuracy over temperature internal soft start 100% duty cycle for low dropout voltage current - mode operation for good line and load transient response 7 a shutdown supply c urrent 235 a quiescent supply current short - circuit and overvoltage protection small 6 - lead tsot package supported by adisimpower ? design tool applications wireless devices 1- to 3 - ce ll li - ion battery - powered applications set - top boxes processor core power supplies hard disk drives general description the adp1864 is a compact, inexpensive, constant - frequency , current - mode , step - down dc - to - dc controller. the adp1864 drives a p - channel mosfet that regulates an output voltage as low as 0.8 v with 1.25 % accuracy, for up to 5 a load currents, from input voltages as high as 14 v. the adp1864 provides system flexibility by allowing accurate setting of the current limit with an external resistor, and the output voltage is easily adjustable using two external resistors. the adp1864 includes an internal soft start to allow quick power - up while preventing input inrush current. additional safety features include short - circuit protection, output o vervoltage protection, and input undervoltage protection. current - mode control provides fast and stable load transient performance, while the 580 khz operating frequency allows a small inductor to be used in the system. to further the life of a battery sou rce, the controller turns on the external p - channel mosfet 100% of the duty cycle during dropout. the adp1864 operates over the ?40c to +125c temperature range and is available in a small, low profile, 6 - lead tsot package. typical applications diagram 05562-001 adp1864 comp gnd fb pgate in cs 174k? 80.6k? 25k? 470pf 1 2 3 5 6 4 68pf 47f 0.03? 10f 2.5v, 2.0a v in = 3.15v to 14v 5h figure 1.
adp1864 data sheet rev. c | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 typical applications diagram ........................................................ 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 4 esd caution .................................................................................. 4 pin configuration and function descriptions ............................. 5 typical performance characteristics ............................................. 6 theory of operation ........................................................................ 8 loop startup .................................................................................. 8 short - circuit protection .............................................................. 9 undervoltage lockout (uvlo) ................................................. 9 overvoltage lockout protection (ovp) .................................... 9 soft start .........................................................................................9 applicatio ns information .............................................................. 10 duty cycle ................................................................................... 10 ripple current ............................................................................ 10 sense resistor .............................................................................. 10 inductor value ............................................................................ 10 mosfet ...................................................................................... 11 diode ............................................................................................ 11 input capacitor ........................................................................... 11 output capacitor ........................................................................ 11 feedback resistors ..................................................................... 11 layout considerations ................................................................... 12 example applications circuits ..................................................... 13 outline dimensions ....................................................................... 14 ordering guide .......................................................................... 14 r evision h istory 8 /1 2 rev. b to rev. c change to features section ............................................................. 1 added adisimpower design tool section ................................. 10 updated outline dimensions ................................ ....................... 14 changes to ordering guide .......................................................... 14 4 /0 8 rev. a to rev. b change general description section ............................................. 1 deleted figure 2 ................................................................................ 1 change to fb regulation voltage parameter ................................ 3 change to mosfet section ......................................................... 11 changes to ordering guide .......................................................... 14 2 /07 rev 0 . to rev. a updated format .................................................................. universal changes to f igure 1 .......................................................................... 1 changes to general description .................................................... 2 changes to specifications ................................................................ 3 change to figure 13 ......................................................................... 8 replaced layout considerations section .................................... 12 replaced example applications circuits s ection ...................... 13 10/05 revision 0: initial version
data sheet adp1864 rev. c | page 3 of 16 specifications v in = 5 v, t j = 25c, unless otherwise noted. table 1. parameter symbol conditions min typ max unit power supply input voltage v in 3.15 14 v quiescent current i q v in = 3.15 v to 14 v, p gate = in 235 360 a shutdown supply current i sd v in = 3.15 v to 14 v, comp = gnd 7 15 a undervoltage lockout threshold v uvlo v in falling, t j = ? 40 c to +12 5c 2.75 2.90 3.01 v v in rising, t j = ? 40 c to +12 5c 2.85 3.00 3.1 5 v error amplifier fb input current i fb v fb = 0.8 v , t j = 25c ?20 ?2 + 20 na v fb = 0.8 v, t j = ? 40 c to +12 5c ?40 ?2 + 40 na amplifier transconductance v fb = 0.8 v, i comp = 5 a 0.24 mm ho comp startup threshold v in = 3.15 v to 14 v , t j = ?40 c to +12 5c 0.55 0.67 0.80 v comp shut down threshold v in = 3.15 v to 14 v , t j = ?40 c to +12 5c 0.15 0.3 0.55 v comp start -u p current source comp = gnd 0.25 0.6 0.95 a fb regulation voltage v in = 3.15 v to 14 v , t j = ?40 c to +12 5c 0.790 0.8 0.81 0 v overvoltage protection threshold v ov p measured at fb , t j = ?40c to +125c 0.87 0.885 0.9 v overvoltage protection hysteresis 50 mv current sense peak current sense voltage t j = ? 40 c to +12 5 c 90 125 mv v in = 3.15 v to 14 v, t j = ? 40 c to +125 c 70 125 mv current sense g ain v cs to v comp 12 v/v output regulation line regulation 1 v in = 3.15 v to 14 v, v fb /v in 0.12 mv/v load regulation 2 v fb /v comp ?2 mv/ v oscillator oscillator frequency v fb = 0.8 v , t j = ?40c to +125c 500 580 650 khz v fb = 0 v 190 khz fb frequency foldback threshold 0.35 v gate drive gate rise time c gate = 3 nf 50 ns gate fall time c gate = 3 nf 40 ns minimum on time pgate minimum low duration 190 ns soft start power - on time 1.1 ms 1 line regulation is measured using the application circuit in figure 1 . line regulation is specified as the change in the fb voltage resulting from a 1 v change in the in voltage. 2 load regulation is measured using the application circuit in figure 1 . load regulation is specified as the change i n the fb voltage resulting from a 1 v change in the comp voltage. the comp voltage range is typically 0.9 v to 2.3 v for the minimum to maximum load current condition.
adp1864 data sheet rev. c | page 4 of 16 absolute m aximum ratings table 2. parameter rating in to gnd ? 0.3 v to +16 v cs, pgate to gnd ? 0.3 v to (v in + 0.3 v) fb, comp to gnd ? 0.3 v to +6 v ja 2- layer (semi standard board) 315 c/w ja 4- layer (jedec standard board) 186 c/w operating junction temperature range ? 40 c to +125 c storage temperature ran ge ? 65 c to +150 c lead temperature rework temperature (j - std - 020b) 260c peak reflow temperature , (20 sec to 40 sec, j - std - 020b) 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect d evice reliability. esd caution
data sheet adp1864 rev. c | page 5 of 16 pin configuration and function descripti ons adp1864 top view (not to scale) com p 1 gnd 2 fb 3 in pga te 6 5 cs 4 05562-003 figure 2 . pin configuration table 3 . pin function descriptions pin o. neonic description 1 comp regulator compensat ion node. comp is the output of the internal transconductance error amplifier. connect a series rc from comp to gnd to compensate for the control loop. add an extra high frequency capacitor between comp and gnd to further reduce switching jitter. the value of this is typically one - tenth of the main compensation capacitor. pulling the comp pin below 0.3 v disables the adp1864 and turns off the external pfet. 2 gnd analog ground. directly connect the compensation and feedback networks to gnd, preferably with a small analog gnd plane. connect gnd to the power ground (pgnd) plane with a narrow track at a single point close to the gnd pin. see the layout considerations section for more information. 3 fb feedback input. connect a resistive voltage divider from the output voltage to fb to set the output voltage. the regulation feedback voltage is 0.8 v. place the feedback resistors as close as possible to the fb pin. 4 cs current sense input. cs is the negative input of the current sense amplifier. it provides the current feedback signal used to terminate the pwm on time. place a current sense resistor between in and cs to set the current limit. the current limit threshold is typically 125 mv. 5 in power input. in is the power suppl y to the adp1864 and the positive input of the current sense amplifier. connect in to the positive side of the input voltage source. bypass in to pgnd w ith a 10 f or larger capacitor as close as possible to the adp1864. for additional high frequency noise reduction, add a 0.1 f capacitor to pgnd at the in pin. 6 pgate gate drive output. pgate drives the gate of the external p - channel mosfet. connect pg ate to the gate of the external mosfet.
adp1864 data sheet rev. c | page 6 of 16 typical performance characteristics 0.810 0.805 0.800 0.795 0.790 ?40 ?20 0 20 40 60 10080 120 05562-004 tempera ture ( c) reference vo lt age (v) v in = 5v figure 3 . reference voltage vs. temperature 600 590 580 570 550 560 ?40 ?20 0 20 40 60 10080 120 05562-005 tempera ture ( c) frequenc y (khz) v in = 5v figure 4 . normalized oscillator frequency vs. temperature 3.10 2.70 ?40 ?20 0 20 40 60 10080 120 05562-006 temperature ( c) v in (v) 3.05 3.00 2.95 2.90 2.85 2.80 2.75 uvlo falling uvlo rising figure 5 . uvlo voltage vs. temperature (v in rising and v in falling) 0.8 0 ?40 ?20 0 20 40 60 10080 120 05562-007 tempera ture ( c) com p (v) 0.7 0.6 0. 5 0.4 0. 3 0.2 0.1 com p f alling com p rising figure 6 . comp shutdown threshold vs. temperature 2.52 2.40 0 3.5 05562-008 load (a) v out (v) 2.50 2.48 2.46 2.44 2.42 0.5 1.0 1.5 2.0 2.5 3.0 figure 7 . typical load regulation (v in = 5 v; see figure 1 ) 2.520 2.500 2.505 2.510 2.515 3 5 7 9 11 13 05562-009 v in (v) v out (v) figure 8. typical line regulation vs. input voltage (see figure 19 )
data sheet adp1864 rev. c | page 7 of 16 12 5 ?40 ?20 0 20 40 60 10080 120 05562-010 temperature (c) shutdown supply current (a) 11 10 9 8 7 6 v in = 5v v in = 3.15v v in = 16v v in = 4v figure 9. shutdown supply current vs. temperature 310 190 ?40 ?20 0 20 40 60 10080 120 05562-011 temperature ( c ) i q ( a) 290 270 250 230 210 v in = 3.1v v in = 4v v in = 5v v in = 7v v in = 12v v in = 16v figure 10 . quiescent current vs. temperature 650 500 3 5 7 11 9 13 05562-012 v in (v) frequenc y (khz) 640 630 620 610 600 590 580 570 560 550 540 530 520 510 temperature = 25c figure 11 . oscillator frequency vs. input voltage
adp1864 data sheet rev. c | page 8 of 16 theory of operation the adp1864 is a constant frequency (580 khz), current - mode buck controller. pgate drives the gate of the extern al p - channel fet . the duty cycle of the external fet dictates the output voltage and the current supplied to the load. the peak inductor current is measured across the external sense resistor, while the system output voltage is fed back through an external resistor divider to the fb pin. at the start of every oscillator cycle, pgate turns on the external fet, causing the inductor current, and therefore the current sense amplifier voltage, to increase. the inductor current increases until the current amplifi er voltage equals the voltage at the comp pin. this resets the internal flip - flop, causing pgate to go high and turning off the external fet. the inductor current decreases until the beginning of the next oscillator period. the voltage at the comp node is the output of the internal error amplifier. the negative input of the error amplifier is the output voltage scaled by an external resistive divider, and the positive input to the error amplifier is driven by a 0.8 v band gap reference. an increase in the load current causes a small drop in the feedback voltage, in turn causing an increase in the comp voltage and , therefore , the duty cycle. the resulting increase in the on time of the fet provides the additional current required by the load. loop start up pu lling the comp pin to gnd disables the adp1864. when the comp pin is released from gnd, an internal 0.6 a current source charges the external compensation capacitor on the comp node. once the comp voltage has charged to 0.67 v, the internal control blocks are enabled and comp is pulled up to its minimum normal operating voltage (0.9 v). as the voltage at co mp continues to increase, the on time of the external fet increases to supply the required inductor current. the loop stabilizes completely once the comp voltage is sufficiently high to support the load current. the regula tion voltage at fb is 0.8 v. icmp r s q rsi slope comp osc frequency foldback 0.35v v in 0.3v gnd comp cs in short-circuit detect 15mv uvlo, switching logic and blanking circuit ovp eamp uvlo vref + 80mv vref 0.8v 2 5 4 v in 0.8v 3 6 fb pgate vref vref 0.8v uvlo shdn uv shdn cmp 0.3v v in 0.6a g s d 2.5v 2a adp1864 05562-013 v in = 3.15v to 14v 1 f igure 12 . functional block diagram
data sheet adp1864 rev. c | page 9 of 16 short - circuit protection if there is a short across the output load, the voltage at the feedback pin (fb) drops rapidly. when the fb voltage drops below 0.35 v, the adp1864 reduces the oscillat or frequency to 190 khz. the increase in the oscillator period allows the inductor additional time to discharge, preventing the output current from running away. once the output short is removed and the feedback voltage increases above the 0.35 v threshol d, the oscillator frequency returns to 580 khz. undervoltage lockout (uvlo) to prevent erratic operation when the input voltage drops below the minimum acceptable voltage, the adp1864 has an undervoltage lockout (uvlo) feature. if the input voltage drops below 2.90 v, pgate is pulled high and t he adp1864 continue s to draw its typical quiescent current. current consump - tion continues to drop toward the shutdown current as input voltage is reduced. the adp1864 is re - enabled and begins switching once the in v oltage is increased above the uvlo rising threshold (3.0 v). overvoltage lockout protection (ovp) the adp1864 provides an overvoltage protection feature to protect the system against output short circuits to a higher voltage supply. if the feedback voltag e increases to 0.885 v, pgate is held high, turning the external fet off. the fet continues to be held high until the voltage at fb decreases to 0.84 v, at which time the adp1864 resumes normal operation. soft start the adp1864 includes a soft start feat ure that limits the rate of increase in the inductor current once the part is enabled. soft start is activated when the input voltage is increased above the uvlo threshold or comp is released from gnd. soft start limits the inrush current at the input and limits the output voltage overshoot. the soft start control slope is set internally.
adp1864 data sheet rev. c | page 10 of 16 applications information adi sim p ower design tool the adp1864 is supported by adisimpower design tool set. adisimpower is a collection of tools that produce complete power designs optimized for a specific design goal. the tools enable the user to generate a full schematic, bill of materials, and calculate performance in min utes. adisimpower can optimize designs for cost, area, efficiency, and parts count while taking into consideration the operating conditions and limitations of the ic and all real external components. for more information about adisimpower design tools, refer to www.analog.com/adisimpower . the tool set is available from this website, and users can also requ est an unpopulated board through the tool. duty cycle to determine the worst - case inductor ripple current, output voltage ripple, and slope compensation factor, establish the system maximum and minimum duty cycle. the duty cycle is calculated by the equat ion ( ) d in d out vv vv dc cycle duty + + = (1) where v d is the diode forward drop. a typical schottky diode has a forward voltage drop of 0.5 v. ripple current choose the peak - to - peak inductor ripple current between 20% and 40% of the maximum load current at the system s highest input voltage. a good starting point for a design is to pick the peak - to - peak ripple current at 30% of the load current. i (peak) = 0.3 i load(max) (2) sense resistor choose the sense resistor value to provide the desired current limit. the inte rnal current comparator measures the peak current (sum of load current and positive inductor ripple current) and compares it against the current limit threshold. the current sense resistor value is calculated by the equation ( ) ( ) ( ) 2 peak max load min sense i i pcsv r ? + = (3 ) whe re pcsv is the peak current sense voltage, typically 0.125 v. to ensure the design provides the required output load current over all system conditions, consider the variation in pcsv over temperature (see the specifications secti on) as well as increases in ripple current due to inductor tolerance. if the system is being operated with >40% duty cycle, incor - porate the slope compensation factor into the calculation. ( ) ( ) ( ) 2 peak max load min sense i i pcsvsf r ? + = (4 ) where sf is the slope factor correction ratio, taken from figure 13 , at the system maximum duty cycle (minimum input voltage). 0 1.0 05562-014 dut y cycle 1.05 0.35 0.95 0.85 0.75 0.65 0.55 0.45 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 slope factor (sf) figure 13 . slope factor (sf) vs. duty cycle inductor value the inductor value choice is important because it dic tates the inductor ripple and, therefore, the voltage ripple at the output. when operating the part at > 40% duty cycle, keep the inductor value low enough for the slope compensation to remain effective. the inductor ripple current is inversely related to t he in ductor value. ( ) ( ) ? ? ? ? ? ? ? ? + + ? =? d in d out out in peak vv vv fl vv i (5) where f is the oscillator frequency. smaller inductor values are usually less expensive, but increase the ripple current and the output voltage ripple. too large an inductor value results in added expense s an d can impede effective load transient responses at >40% duty cycle because it reduces the effect of slope compensation. start with the h ighest input voltage, and assuming the ripple current is 30% of the maximum load cu rrent, ( ) ( ) ? ? ? ? ? ? ? ? + + ? = d in d out max load out in vv vv f i vv l 3.0 (6) f rom this starting point, modify the inductance to obtain the right balance of size, cost, and output voltage ripple , while maintaining the inductor ripple current between 20% and 40% of the maximum load current.
data sheet adp1864 rev. c | page 11 of 16 mosfet choose the external p - channel mosfet based on the following: threshold voltage (v t ), maximum voltage and current ratings, r ds(on) , and gate charge. the minimum operating voltage of the adp1864 is 3.15 v. choose a mosfet with a v t that is at least 1 v lower than the minimum input supply voltage used in the application. ensure that the maximum ratings for mosfet v sg and v sd a re a few volts greater than the maximum input voltage used with the adp1864. estimate the rms current in the mosfet under continuous conduction mode by ( ) load din d out rms fet i vv vv i + + = (7) derate the mosfet current by at least 20% to account for inductor ripple and changes in the diode voltage. the mosfet power dissipation is the sum of the conducted and switching losses: pd fet(cond) = ( i fet(rms) ) 2 (1 + t ) r ds(on) (8 ) where t = 0.005/ c t j (fet) ? 25c . ensure the maximum power d issipation calculated is signif icantly less than the maximum rating of the mosfet. diode the diode carries the inductor current during the off time of the external fet. the average current of the diode is, therefore, depe ndent on the duty cycle of the controller as well as the output load current. ( ) load d in d out av diode i vv vv i ? ? ? ? ? ? ? ? + + ?= 1 (9) where v d is the diode forward drop. a typical schottky diode has a forward drop voltage of 0.5 v . a schottky diode is recommended for best efficienc y because it has a low forward drop and faster switching speed than junction diodes. if a junction diode is used it must be an ultrafast recovery diode. the low forward drop reduces power losses during the fet off time, and fast switching speed reduces the switching losses during pfet transitions. input capacitor the input capacitor provides a low impedance path for the pulsed current drawn by the external p - channel fet. choose an input capacitor whose impedance at the switching frequency is lower than t he impedance of the voltage source (v in ). the preferred input capacitor is a 10 f ceramic capacitor due to its low esr and low impedance. for all types of capacitors, make sure the ripple current rating of the capacitor is greater than half of the maximum output load current. where space is limited, multiple capacitors can be plac ed in parallel to meet the rms current requirement. place the input capacitor as close as possible to the in pin of the adp1864. output capacitor the esr and capacitance value of the output capacitor determine the amount of output voltage ripple. ? ? ? ? ? ? ? ? + ??? c esr cf iv out out 8 1 (10 ) where f is the oscillator frequency (typically 580 khz). because the output capacitance is typically >40 f, the esr dominates the voltage ripple. ensure the output capacitor ripple rating is greater than the maximum inductor ripple. ( ) ( ) ? ? ? ? ? ? ? ? ?+ ? in out in d out rms vfl vvvv i 32 1 (1 1) poscap ? capacitors from sanyo offer a good size, esr, ripple, and current capability trade - off. feedback resistors the feedback resistor s ratio sets the output voltage of the system. adp1864 fb 3 r1 v out r2 05562-015 figure 14 . two feedback resistors used to set output voltage 2 2 vv out rr1 r + = 8.0 (12 ) ( ) 8.0 8.0 ? = out v r2r1 (13 ) choose 80.6 k? for r2. using higher values for r2 results in reduced output voltage accuracy , and lower values cause an increased voltage divider current, thus increasing quiescent current consumption.
adp1864 data sheet rev. c | page 12 of 16 layout consideration s layout is important with all switching regulators, b ut is particu - larly important for high switching frequencies. ensure all high current paths are as wide as possible to minimize track induc - tance, which causes sp iking and electromagnetic inter ference (emi). these paths are shown in bold in figure 15 . place the current sense resistor and the input capacitor(s) as close to the in pin as possible. keep the pgnd connections for the diode, input capacitor(s), and output capacitor(s) as close together as possible on a wide pgnd plane. connect the pgnd and gnd planes at a single point with a narrow trace close to the adp1864 gnd connection. ensure the feedback resistors are placed as close as possible to the fb pin to prevent stray pickup. to prevent extra noise pickup on the fb line, d o not allow the feedback trace from the output voltage to fb to pass right beside the drain of the external pfet. add an extra copper plane at the connection of the fet drain and the cathode of the diode to help dissipate the heat generated by losses in t hose components. all analog compo nents are grouped together on the left side of the evaluation board (left side of the adp1864 dut , see figure 16) , including compensation and fb components . all power components are located on the right side of the board ( mosfet, i nductor, i nput bypass capacitors, o utput capacitors , and power diode). all n oisy nodes (p - channel drain, power diode cathode , and inductor terminal) are located along the bottom portion of the eval uation board on the top layer ( see figure 16). a s ubstantial amount of copper has been allocated for this area with ample track spac ing to minimize coupling (cross talk) effects during switching. the fb tap is isolated and runs from the r top , along the u pper right portion of the board on the bottom layer ( see figure 17) to minimize emi pickups emitted from the power components along the bottom portion of the evaluation board s top layer ( see figure 16 ). sufficient track spac ing is placed from the main power ground p lane located near the center of the board to effectively decouple this track . there are two ground planes on the top layer: the a nalog g round plane is on the left and the p ower ground plane on the right. an analo g ground pick up point projects down to the bottom layer and through a single narrow and isolated track ( see figure 17). the p - ch annel gate should have an isolated trace (bottom layer ) tying back to p in 6 of the dut by via connections. adp1864 comp gnd fb cs pgate in 1 2 3 5 6 4 v in v out pgnd ce1 ce2 r2 c2 c1 r s r top r bottom 05562-016 u1 d1 l1 figure 15 . application circuit showing high current paths (in bold) 05562-020 r2 r s c1 ce1 ce2 d1 u1 l1 c2 r bottom r top fb tap analog ground tap noisy power plane is located on this side of the board to accomodate spiky nodes and minimize emi effects to the rest of the system. isolated power ground plane. use a substantial amount of copper to best accommodate this high current path. also provides aid for power dissipation. v out figure 16 . top layer of an example layout for an adp1864 application 05562-021 1 fb tap from output to r top . trace should be away from power components to minimize emi pickup. 3 isolated track for connecting agnd to pgnd. this helps minimize stray parasitic effects towards the analog components (fb and compensation components). 2 isolated trace for gate connection of the pfet. routing of this connection away from the cathode of d1 and drain of pfet is to ensure that noise does not couple into this track. 2 1 3 figure 17 . bottom layer of an example layout of an adp1864 application
data sheet adp1864 rev. c | page 13 of 16 example applications circuits adp1864 comp gnd fb pgate in cs 255k ? 80.6k ? 25k ? 470pf 1 2 3 5 6 4 05562-018 rsense lrc-lr1206-01-r030-f mosfet fairchild semi fdc638p inductor toko fdv0630-3r3m diode synsemi sk22 cin lmk325bj106kn cout sanyo poscap 6tpb47m 68pf 47 f 0.03 ? 10 f 3.3v, 2.0a v in = 4.5v to 5.5v 3.3 h figure 18. application circuit for v out = 3.3 v, 2 a load 05562-019 rsense lrc-lr1206-01-r030-f mosfet fairchild semi fdc658p inductor sumida cdrh6d38-5r0 diode vishay ssb43l cin lmk325bj106kn cout sanyo poscap 6tpb47m adp1864 comp gnd fb pgate in cs 174k? 80.6k? 25k? 470pf 1 2 3 5 6 4 68pf 47f 0.03? 10f 2.5v, 2.0a v in = 3.15v to 14v 5h figure 19 . application circuit for v out = 2.5 v , 2 a load
adp1864 data sheet rev. c | page 14 of 16 outline dimensions 102808- a * compliant to jedec standards mo-193-aa with the exception of package height and thickness. 1 3 45 2 6 2.90 bsc 1.60 bsc 2.80 bsc 1.90 bsc 0.95 bsc 0.10 max * 1.00 max pin 1 indic at or * 0.90 0.87 0.84 0.60 0.45 0.30 0.50 0.30 0.20 0.08 sea ting plane 8 4 0 figure 20 . 6 - lead thin small outline transistor package [tsot] (uj- 6) dimensions shown in millimeters ordering guide model 1 , 2 temperature range package description package option branding adp1864 aujz - r7 ? 40 c to +125c 6 - lead thin small o utline transistor package [tsot] uj - 6 p0n adp1864 - eval evaluation board adp1864 - evalz evaluation board 1 z = rohs compliant part. 2 v out = 2.5 v (variable), i load = 0 a to 3 a, v in = 3.15 v to 14 v.
data sheet adp1864 rev. c | page 15 of 16 notes
adp1864 data sheet rev. c | page 16 of 16 notes ? 2005 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05562 -0- 8/12(c)

▲Up To Search▲

Price & Availability of ADP1864-15

	To Download ADP1864-15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .